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AN1696 Scheda tecnica(PDF) 8 Page - STMicroelectronics |
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AN1696 Scheda tecnica(HTML) 8 Page - STMicroelectronics |
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8 / 11 page ![]() AN1696 APPLICATION NOTE 8/11 Figure 5. Adjustment network 2.3 Gate driver of OR-ing FET The OR-ing FET gate is driven by the output of a comparator (one section of an LM293, standard double com- parator) sensing the voltage upstream (source) and downstream (drain) the OR-ing FET (see fig. 6). This turns- off the transistor whenever a current tries flowing from the load towards the output stage of a daughter board. Whenever one section is enabled with the two others already running (hot plug), its output capacitor is com- pletely discharged: to avoid a negative drop on the load voltage, the gate of the FET is kept low until VC(OUT) reaches a value very close to VLOAD (this can be set defining the ratio between R5 and R7). The PWM starts charging output capacitor (VC(OUT) increases) and, only when: the FET is turned on. Moreover the load must be isolated from a failed section; for example in case of a short circuit on the low side power MOS of one section, then a current will tend to flow in reverse direction through the corresponding OR- ing FET. Figure 6. OR-ing FET management V OUT = +3.3V R A ADJ R 13 + - I ADJ L6615 MOTHERBOARD DAUGTHERBOARD L6910 V FB R 8 R 6 R 7 C 10 V OUT = +3.3V R A ADJ R 13 + - I ADJ L6615 MOTHERBOARD DAUGTHERBOARD L6910 V FB R 8 R 6 R 7 C 10 V CO UT () ON – V REF 1 R5 R7 -------- + ⋅ V LO AD R8 R8 R9 + ---------------------- 1 R5 R7 -------- ⋅ ⋅⋅ == L O A D - + R8 R9 C2 R7 DAUGHTERBOARD MOTHERBOARD R5 V C(OUT) V LOAD V REF V PS+ V GATE V REF V C(OUT) V PS+ V GATE ∆V HYST V PUMP V C(OUT)-ON V C(OUT)-OFF V LOAD SECTIONS ALREADY RUNNING R11 V PUMP PUMP CHARGE L O A D L O A D - + R8 R9 C2 R7 DAUGHTERBOARD MOTHERBOARD R5 V C(OUT) V LOAD V REF V PS+ V GATE V REF V C(OUT) V PS+ V GATE ∆V HYST V PUMP V C(OUT)-ON V C(OUT)-OFF V LOAD SECTIONS ALREADY RUNNING R11 V PUMP PUMP CHARGE |
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