2-Level turn-off

AN2123

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6 2-Level turn-off

In the event of a short-circuit or overcurrent in the load, a large voltage overshoot can occur across the

IGBT at turn-off and can exceed the IGBT breakdown voltage. By reducing the gate voltage before turn-

off, the IGBT current is limited and the potential over-voltage is reduced. This technique is called 2-level

turn-off. Both the level and duration of the intermediate off level are adjustable. The duration is set by an

external resistor/capacitor in conjunction with the integrated voltage reference for accurate timing. The

level can be easily set by an external Zener diode, and its value is chosen depending upon the IGBT’s

characteristics. This 2-level turn-off sequence takes place at each cycle; it has no effect if the current

doesn’t exceed the normal maximum rated value, but protects the IGBT in case of overcurrent (with a

slight increase to conduction losses).

The principle is shown on Figure 12. During the 2-level turn-off time, the OUT pin is controlled by a

comparator between the actual OUT pin and an external reference voltage. When the voltage on OUT

goes down as a result of the turn-off and reaches the reference threshold, then the OUT output is

disabled and the IGBT gate is discharged no further. After the 2-level turn-off delay, the OUT output is

enabled again to end the turn-off sequence.

To keep the output signal width unchanged relative to the input signal, the turn-on is delayed by the same

value than the 2-level turn-off delay (see Figure 13).

The duration of the 2-level turn-off is set by the external Rd-Cd components, and is approximately given

by the formula:

delay from about 0.7 to 6.6 microseconds.

Figure 12. Principle schematic for 2-level turn-off feature

Control

Block

120µA

VREF

VH

3

2,5V

4

CD

LVOFF

7

6

OUT

VL

Lvoff

off