SPV1040 parallel and series connection

AN3319

22/25

DocID18265 Rev 8

Therefore:

For example, assuming P

OUT

= 3 W and V

OUT

= 12 V, then

V

OUTx

= 4 V.

Lower irradiation for one panel, for example on panel 2, causes lower output power, so

lower V

OUT2

due to the I

OUT

imposed by the topology:

The output voltage required by the load can be provided by the 1

st

and the 3

rd

SPV1040 but

only up to the limit imposed by each of their R

1

/R

2

partitionings.

Some examples can help in understanding the various scenarios assuming that each R

1

/R

2

limits V

OUTx

to 4.8 V.

Example 1:

Panel 2 has 75 % irradiation of panels 1 and 3:

Two SPV1040s (1

st

and 3

rd

) supply the voltage drop caused by the lower irradiation on

panel 2.

Warning:

transferred to the output stage through the integrated P-

channel MOS without entering the switching mode.

OUT

OUTx

V

3

1

V

=

OUT

OU Tx

OUTx

I

P

V

=

3

OUT

1

OUT

2

OUT

V

*

4

3

V

*

4

3

V

=

=

W

1

P

P

3

OUT

1

OUT

=

=

W

75

.

0

P

4

3

P

1

OU T

2

OUT

=

=

W

75

.

2

P

P

P

P

3

OUT

2

OUT

1

OUT

OUT

=

+

+

=

A

23

.

0

12

75

.

2

V

P

I

OUT

OUT

OUT

=

=

=

V

35

.

4

23

.

0

1

V

V

3

OUT

1

OUT

=

=

=

V

26

.

3

23

.

0

75

.

0

V

2

OUT

=

=