LED power-on at maximum current and 50% duty cycle

AN4374

10/25

DocID025366 Rev 2

Figure 9. Channel data and write switch

To carry on the changes both on the configuration register and on brightness register, the

patterns are shown in Figure 10, Figure 11 and Figure 12.

Figure 10. LED1642GW and ALED1642GW configuration register

•

In Figure 11 and Figure 12, as in the previous example, a 16-bit value has to be sent for

each of 16 outputs, in particular, the first 15 patterns have a data latch (LE high for 3

CLK rising edges), last pattern has a global latch (LE high for 5 CLK rising edges).

Unlike the first example, this time, the value to be programmed is 0x0800 to get 50%

PWM duty cycle (12-bit counter) for all driver outputs:

CFG-14

Gradual output

delay

R/W

“0” a progressive delay is applied to output (10 ns per

channel)

”1” no delay is applied to output

0

CFG-15

12/16 PWM

counter

R/W

“0” to select 16-bit brightness register (65536 grayscale

rightness steps).

“1” to select 12-bit brightness register (4096 grayscale

brightness steps)

0

Table 3. Configuration register (continued)

Bit

Definition

R/W

Description

Default

0E

0F

0C

0A

0B

0D

09

08

07

06

05

04

03

02

01

00

CLK

SDI

LE

16-bit data

AM16858v1

Clk

SDI

LE

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

first bit

last bit

CFG reg. in default condition except CFG -15/6 to 0=1: 12 bit PWM counter/gain=max/range=1

(CFG reg.= 0x807F)

traces are

overlapped

Data signal is high for clock rising edges 15, 06 to 00; LE is high for 7 clock rising edges

AM16859v1