AN4496 datasheet(6/18 Pages) STMICROELECTRONICS

6 / 18 page

ILED pin

AN4496

6/18

DocID026370 Rev 1

The selected value of VR and VINmin imposes the maximum value of:

Equation 8

Where VINmin is the minimum RMS input voltage and  is the efficiency at the VIN used in

the equation.

The correct AC modulation is obtained setting the voltage divider ratio (KAC) equal to:

Equation 9

Where Vdrp is the input drop voltage between VIN and VRECT (input bridge, input filter, fuse,

etc.).

Referring Figure 2 on page 1, because KAC is >> 1, then Rp3 can be set equal to RAC:

Equation 10

Rp1 + Rp2 = Rp3 * (KAC - 1)

1.3

High power factor implementation in wide input range

application

With the value of the components chosen in the previous paragraph, the AC modulation is

optimized at the minimum input voltage. When the voltage increases, the ILED pin average

voltage decreases, but the AC modulation increases and forces to zero the primary current

for longer time near the zero crossing (see Figure 3 B). The effect is the generation on the

input current a zero crossing distortion, that initially, reduces the harmonics (and THD) of the

flyback configuration, but when the input voltage reaches a value around 1.25 * VINmin, the

distortion begins again to increase. If is desired a THD under 20 - 25%, the ratio between

the maximum and minimum of VIN must be lower than 1.5.

In Figure 6 is presented a solution that permit to cover wide-range application with THD

under 20 - 25% and high PF. The circuitry uses in the low range (USA and Japan) a different

voltage divider ratio (KAC), than in the high range (European). The transistor Qr is used to

change the voltage divider ratio between the value KACL in the US and Japanese and KACH

in the European range.

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