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AN2053 Scheda tecnica(PDF) 4 Page - STMicroelectronics

Il numero della parte AN2053
Spiegazioni elettronici  SLIC protection for both classical and new networks
PDF  15 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2053 Scheda tecnica(HTML) 4 Page - STMicroelectronics

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LCP concept
AN2053
4/15
Doc ID 10917 Rev 2
2
LCP concept
Figure 5.
LCP15xx concept behavior
Figure 5 shows the classical protection circuit using the LCP15xx crowbar concept. This
topology has been developed to protect the new high voltage SLICs. It allows the system to
be programmed for the negative firing threshold while the positive clamping value is fixed at
GND.
When a negative surge occurs on one wire (L1 for example), a current Ig flows through the
base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 turns
on and all the surge current is short circuited to ground. After the surge, when the current
flowing through Th1 becomes lower than the holding current Ih, then Th1 switches off.
When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the
surge current is short circuited to ground.
In order to minimize the remaining voltage across the SLIC inputs during the surge, a 4 point
structure has been implemented (Pins 1 and 8 for TIP / Pins 4 and 5 for RING). This fact
allows the board designer to connect the track as designed in Figure 6. With such a PCB
design, extra voltages caused by track stray inductance and current slope (Ldi/dt) remain
located on the line side of the LCP and do not affect its SLIC side.
The capacitor C is used to speed up the crowbar structure firing during the fast negative
surge edges. This allows the dynamic breakover voltage at the SLIC Tip and Ring inputs to
be minimized during fast strikes. Please note that this capacitor is generally present around
the SLIC -Vbat pin. So to be efficient it has to be moved as close as possible to the LCP15xx
Gate pin and to the reference ground track (or plan) (see Figure 6). Optimized value for C is
220 nF.
V Ring
GND
Gate
TIP
RING
GND
-Vbat
C
Rs1
Rs2
L 1
L 2
V Tip
Th1
D1
T1
Ig
ID1



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