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AN4192 Scheda tecnica(PDF) 40 Page - STMicroelectronics |
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AN4192 Scheda tecnica(HTML) 40 Page - STMicroelectronics |
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40 / 47 page ![]() Low-side FET selection AN4192 40/47 Doc ID 023820 Rev 1 Subsequently, the external HS gate resistor becomes 2.2 Ω, while the other components remain unchanged (“Configuration 2”). A further reduction of the phase node spike is achieved (30.1 V). In Figure 50, the waveforms at full load conditions are reported. Finally, the snubber resistor value is decreased from 1.8 Ω to 1 Ω, to emphasize the CSNUB effect (“Configuration 3”). The gate resistors are unmodified (Figure 51). Figure 50. RG,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ original snubber waveforms @ 20 A AM16493V1 |
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