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UPD4724 Scheda tecnica(PDF) 2 Page - NEC |
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UPD4724 Scheda tecnica(HTML) 2 Page - NEC |
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2 / 16 page ![]() 2 µPD4724 BLOCK DIAGRAM/PIN CONFIGURATION (TOP VIEW) C1 + VDD VCC C1 – C5 + GND C4 + GND C4 – VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C3 +10 V C1 C5 +3.3 V or +5 V DIN1 DIN2 DIN3 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 DOUT1 DOUT2 DOUT3 RIN1 RIN2 RIN3 RIN4 RIN5 Note EN VCHA STBY –10 V C2 C4 300 Ω 300 Ω 300 Ω 5.5 k Ω 5.5 k Ω 5.5 k Ω 5.5 k Ω 5.5 k Ω + + + + + C5 – Note The pull-up resistors of the driver inputs are active resistors. Remark 1. VDD and VSS are pins that output the voltage boosted internally. Don't connect these pins to the load. 2. Capacitors with a breakdown voltage of 20 V or higher are recommended for C1 to C5. And it is recommended to insert the capacitor that is 0.1 µF to 1 µF between VCC and GND. 3. The capacitor C5 does not have to be connected when the IC is used in 5 V mode (VCHA = L). |
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