PM0222 datasheet(8/33 Pages) STMICROELECTRONICS

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Clock configurations

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Clock configurations

3.1

Peripheral clock gating

Brain provides a functional clock gating for each peripheral through the CRMU register

CCR2. This allows saving power consumption by activating the clock only when a peripheral

is in use. It is the role of the software to deactivate the clock of each peripheral as soon as

the peripheral is not in use. After a reset, all peripheral clocks are disabled. For more details,

see Brain reference manual, CRMU registers chapter, CRMU_CCR2 description.

3.2

CPU clock configuration

Changing the CPU clock also impacts the GPIO, SPI and Timer clocks, thus changing

data/count rates in these peripherals. For more details about clock generation logic, see

Brain reference manual, §5.2.1 - Generic description.

3.2.1

Flash wait states

When changing the CPU clock, the software must also change the Flash wait states

accordingly before the next Flash read access. Wait states and REGISTERED values to

program according to the CPU clock frequency are provided in a table in the Brain reference

manual, Embedded Flash memory chapter, CONFIG register description.

Executing from Flash

When executing from Flash, it is mandatory to adjust the number of wait states before

changing the CPU clock because Cortex-M0 continuously fetches instructions from Flash.

The correct sequence is:

Increase CPU clock frequency:

–

Set a number of wait states allowed for the new clock frequency by writing to the

FLASH.CONFIG register (see Brain reference manual, Embedded Flash memory

chapter, CONFIG register description)

–

Set the new higher clock frequency by writing to the CRMU.CCR0 register

Decrease CPU clock frequency:

–

Set the new lower clock frequency by writing to the CRMU.CCR0 register

–

Set a number of wait states allowed for the new clock frequency by writing to the

FLASH.CONFIG register (see Brain reference manual, Embedded Flash memory

chapter, CONFIG register description)

Executing from RAM

When executing from RAM, no Flash wait state adjustment is necessary when changing the

CPU clock until the software needs to read data from Flash in which case, it must:

–

either go back to a lower clock frequency compatible with the current wait state

configuration (FLASH.CONFIG register)

–

or set a wait state configuration compatible with the current clock frequency

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