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AN1014 Scheda tecnica(PDF) 4 Page - STMicroelectronics

Il numero della parte AN1014
Spiegazioni elettronici  HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
PDF  25 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN1014 Scheda tecnica(HTML) 4 Page - STMicroelectronics

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HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
3 POWER MANAGEMENT MODES
The ST7 can run in the following six main modes:
3.1 STANDARD RUN MODE
This mode is the normal operation of any MCU, where
fCPU = fOSC2 = fOSC/2 (when PLL is disabled by OPTION BYTE).
fOSC2 = fOSC*2 (when PLL is enabled by OPTION BYTE).
So, the consumption varies depending on whether the PLL is disabled or enabled.
3.2 SLOW MODE
This mode is controlled by three bits in the MCCSR register: the SMS bit which enables or dis-
ables Slow mode and two CPx bits which select the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16.
The CPU and peripherals are clocked at this lower frequency (fCPU). The configuration for
clock frequency is:
fCPU = fOSC2 / 2, 4, 8, 16
= fOSC / 4, 8, 16 or 32 (when PLL is disabled by OPTION BYTE).
Uses:
- To reduce the power consumption by decreasing the internal clock in the device.
- To adapt the internal clock frequency to the available supply voltage.
3.3 WAIT MODE
In this mode, the CPU is stopped and the peripherals are still running at standard fCPU. It is se-
lected by calling the ‘WFI’ instruction. All peripherals remain active.
During WAIT mode, the I[1:0] bits in the CC register are forced to ‘10’, to enable all interrupts.
All other registers and memory remain unchanged. The MCU remains in WAIT mode until an
interrupt or RESET occurs, whereupon the Program Counter branches to the starting address
of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or
an Interrupt occurs, causing it to wake up.
Uses:
- To place the MCU in low power consumption mode by stopping the CPU.
- External interrupt capability with all peripherals remaining active
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