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LTC2053 Scheda tecnica(PDF) 5 Page - Linear Technology |
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LTC2053 Scheda tecnica(HTML) 5 Page - Linear Technology |
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5 / 18 page ![]() LTC2053/LTC2053-SYNC 2053syncfc INPUT COMMON MODE VOLTAGE (V) 0 15 10 5 0 –5 –10 –15 0.5 1.0 1.5 2.0 2053 G01 2.5 3.0 VS = 3V VREF = 0V TA = 25°C G = 1000 G = 100 G = 10 G = 1 INPUT COMMON MODE VOLTAGE (V) 0 15 10 5 0 –5 –10 –15 1 2 3 4 2053 G02 5 VS = 5V VREF = 0V TA = 25°C G = 1000 G = 100 G = 10 G = 1 INPUT COMMON MODE VOLTAGE (V) –5 20 15 10 5 0 –5 –10 –15 –20 –3 –1 1 3 2053 G03 5 VS = ±5V VREF = 0V TA = 25°C G = 1000 G = 10 G = 1 G = 100 INPUT COMMON MODE VOLTAGE (V) 20 15 10 5 0 –5 –10 –15 –20 2053 G04 0 0.5 1.0 1.5 2.0 2.5 3.0 VS = 3V VREF = 0V G = 10 TA = 25°C TA = 85°C TA = 70°C TA = –55°C INPUT COMMON MODE VOLTAGE (V) 0 20 15 10 5 0 –5 –10 –15 –20 1 2 3 4 2053 G05 5 VS = 5V VREF = 0V G = 10 TA = 25°C TA = 85°C TA = –55°C TA = 70°C INPUT COMMON MODE VOLTAGE (V) –5 20 15 10 5 0 –5 –10 –15 –20 –3 –1 1 3 2053 G06 5 VS = ±5V VREF = 0V G = 10 TA = 25°C TA = 85°C TA = –55°C TA = 70°C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels in high speed automatic test systems. VOS is measured to a limit determined by test equipment capability. Note 3: If the total source resistance is less than 10k, no DC errors result from the input bias currents or the mismatch of the input bias currents or the mismatch of the resistances connected to –IN and +IN. elecTrical characTerisTics Note 4: The CMRR with a voltage gain, AV, larger than 10 is 120dB (typ). Note 5: At temperatures above 70°C, the common mode rejection ratio lowers when the common mode input voltage is within 100mV of the supply rails. Note 6: The power supply rejection ratio (PSRR) measurement accuracy depends on the proximity of the power supply bypass capacitor to the device under test. Because of this, the PSRR is 100% tested to relaxed limits at final test. However, their values are guaranteed by design to meet the data sheet limits. Input Offset Voltage vs Input Common Mode Voltage Input Offset Voltage vs Input Common Mode Voltage Typical perForMance characTerisTics Input Offset Voltage vs Input Common Mode Voltage Input Offset Voltage vs Input Common Mode Voltage Input Offset Voltage vs Input Common Mode Voltage Input Offset Voltage vs Input Common Mode Voltage |
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