AN1775 datasheet(13/27 Pages) STMICROELECTRONICS

13 / 27 page

AN1775

5 Debug management

13/27

For more details on the JTAG port refer to the IEEE standard 1149.1-1993, “Standard Test

Access Port-Scan Boundary Architecture” specification.

RTCK

GND

(not used)

Return TCK (to

JTAG

equipment)

Some devices sample TCK (for example a synthesizable core

with only one clock), and this has the effect of delaying the

time that a component actually captures data. Using a

mechanism called adaptive clocking, the RTCK signal is

returned by the core to the JTAG equipment, and the clock is

not advanced until the core had captured the data. In adaptive

clocking mode, the debugging equipment waits for an edge on

RTCK before changing TCK.

TDO

JTDO

Test data out (to

JTAG

equipment)

TDO is the return path of the data input signal TDI.

nSRST

nRSTIN

System reset

(bidirectional)

nSRST is an active LOW open-collector signal that can be

driven by the JTAG equipment to reset the target board. Some

JTAG equipment senses this line to determine when a board

has been reset by the user.

When the signal is driven LOW by the reset controller on the

core module, the motherboard resets the whole system by

driving nSYSRST low.

DBGRQ

DBGRQS

(not used

w/ 64pin)

Debug request

(from JTAG

equipment)

DBGRQ is a request for the processor core to enter debug

state.

DBGACK

GND

(not used)

Debug

acknowledge

(to JTAG

equipment)

DBGACK indicates to the debugger that the processor core

has entered debug mode.

Std Name

STR71x

Description

Function

AN1775 Scheda tecnica(PDF) 13 Page - STMicroelectronics

AN1775 Scheda tecnica(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Scheda tecnica Scarica

Link URL