AN2014 datasheet(7/65 Pages) STMICROELECTRONICS

7 / 65 page

DocID10701 Rev 10

7/65

AN2014

EEPROM cell and memory array architecture

1.1

Floating gate operation within an EEPROM cell

From the user’s point of view, this EEPROM device is a circuit for storing digital information.

To interface with the EEEPROM device a set of standard instructions are used. Behind this

simple interface, however, there are a number of sensitive analog and physical processes.

Figure 1. Structure of an EEPROM floating gate transistor, and circuit symbol

Figure 1. shows the key component of a single EEPROM cell, the floating gate transistor

(also known as a FLOTOX transistor). Figure 2. shows how it can be considered to be just

like any other type of MOSFET device. As the voltage, Vg, is increased on the Control Gate

electrode, so the current flowing through the drain, Id, increases in proportion. For the

present, we can assume that this is a fairly linear relationship.

Figure 2. MOSFET-like operation

Figure 3 shows what happens if the floating Gate can be made more negatively charged, by

filling it with extra electrons. This is used for the Erased state of the EEPROM cell. Figure 4

shows what happens if the floating Gate can be made less negatively charged, by emptying

it some of its normal electrons. This is used for the Written state of the EEPROM cell.

AI10227

Tunnel Oxide

Control Gate

Floating Gate

Source

Drain

Gate Oxide

Oxide

Channel Region

Drain

Source

Control Gate

Floating Gate

AN2014 Scheda tecnica(PDF) 7 Page - STMicroelectronics