Clocks

AN2586

14/28

Doc ID 13675 Rev 7

2.3

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is

enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

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If a failure is detected on the HSE oscillator clock, the oscillator is automatically

disabled. A clock failure event is sent to the break input of the TIM1 advanced control

timer and an interrupt is generated to inform the software about the failure (clock

security system interrupt CSSI), allowing the MCU to perform rescue operations. The

CSSI is linked to the Cortex™-M3 NMI (non-maskable interrupt) exception vector.

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If the HSE oscillator is used directly or indirectly as the system clock (indirectly means

that it is used as the PLL input clock, and the PLL clock is used as the system clock), a

detected failure causes a switch of the system clock to the HSI oscillator and the

disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the

clock entry of the PLL used as system clock when the failure occurs, the PLL is

disabled too.

For details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference

manuals available from the STMicroelectronics website www.st.com.