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AN3265 Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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AN3265 Scheda tecnica(HTML) 10 Page - STMicroelectronics |
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10 / 19 page ![]() Software description AN3265 10/19 Doc ID 17860 Rev 1 2.1.4 CLK The clock control enables and delivers the correct clock frequency to the CPU and peripherals. It configures the HSI and HSE prescalers division factor from 8 to 1. 2.1.5 GPIOs The application drives the MCU I/Os to interface the microcontroller with external hardware components, i.e. the LEDs and the pushbuttons. 2.1.6 EXTI The external interrupt sensitivity is configured to trigger an interrupt each time a falling edge, and only a falling edge, is detected on PB0. 2.1.7 Data EEPROM The SystemState variable represents the current state of the application. It is stored in the STM8S105C6T6 data EEPROM thus allowing to save the application progress in the state machine when the microcontroller is reset (see Figure 5). 2.1.8 RST The reset register (RST_SR) is used in conjunction with the IWDG and WWDG to determine which of them has triggered a reset. 2.1.9 CCO The Configurable clock output register (CLK_CCOR) allows to select the clock source that is output on the CCO pin. 2.2 Exclusion of the Standard STM8S standard firmware library As this application uses optimized code, the stm8s.h file must be modified not to include the STM8S standard firmware library. This is done by commenting the following define statement: #define USE_STDPERIPH_DRIVER |
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