AN3422 datasheet(23/52 Pages) STMICROELECTRONICS

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AN3422

Peripheral migration

Doc ID 018976 Rev 2

23/52

Peripheral access configuration: since the address mapping of some peripherals has

been changed in L1 series vs. F1 series, you need to use different registers to

[enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode].

To configure the access to a given peripheral you have first to know to which bus this

peripheral is connected, refer to Table 4 on page 15, then depending on the action needed

you have to program the right register as described in Table 8 above. For example, USART1

is connected to APB2 bus, to enable the USART1 clock you have to configure APB2ENR

RCC->APB2ENR |= RCC_APB2ENR_USART1EN;

to disable USART1 clock during Sleep mode (to reduce power consumption) you have to

configure APB2LPENR register as follows:

RCC->APB2LPENR |= RCC_APB2LPENR_USART1LPEN;

Peripheral clock configuration: some peripherals have a dedicated clock source

independent from the system clock, and used to generate the clock required for their

operation:

USB: The USB 48 MHz clock is derived from the PLL VCO clock which should be

at 96MHz

SIDO: The SDIO clock (SDIOCLK) is derived from the PLL VCO clock and is equal

to PLLVCO / 2

LCD: The LCD Glass clock shares the same clock source as the RTC

ADC: in STM32L1 series the ADC features two clock schemes:

–

Clock for the analog circuitry: ADCCLK. This clock is always the HSI oscillator

clock. A divider by 1, 2 or 4 allows to adapt the clock frequency to the device

operating conditions. This configuration is done using ADC_CCR[ADCPRE] bits.

The ADC Clock depends also on the voltage range VCORE. When product voltage

Table 8.

RCC registers used for peripheral access configuration

Bus

Comments

AHB

RCC_AHBRSTR

Used to [enter/exit] the AHB peripheral from reset

RCC_AHBENR

Used to [enable/disable] the AHB peripheral clock

RCC_AHBLPENR

Used to [enable/disable] the AHB peripheral clock in low

power Sleep mode

APB1

RCC_APB1RSTR

Used to [enter/exit] the APB1 peripheral from reset

RCC_APB1ENR

Used to [enable/disable] the APB1 peripheral clock

RCC_APB1LPENR

Used to [enable/disable] the APB1 peripheral clock in low

power Sleep mode

APB2

RCC_APB2RSTR

Used to [enter/exit] the APB2 peripheral from reset

RCC_APB2ENR

Used to [enable/disable] the APB2 peripheral clock

RCC_APB2LPENR

Used to [enable/disable] the APB2 peripheral clock in low

power Sleep mode

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