RM0312 datasheet(148/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

148/275

DocID022352 Rev 3

17.7.5

Interrupt enable register (TIMx_IER)

Address offset: 0x04

Reset value: 0x00

17.7.6

Status register 1 (TIMx_SR1)

Address offset: 0x05

Reset value: 0x00

654

3210

BIE

TIE

Reserved

CC2IE

CC1IE

UIE

Bit 7 BIE: Break interrupt enable

0: Break Interrupt disabled.

1: Break Interrupt enabled.

Bit 6 TIE: Trigger Interrupt Enable.

0: Trigger Interrupt disabled.

1: Trigger Interrupt enabled.

Bits 5:3 Reserved

Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 Interrupt disabled

1: CC2 Interrupt enabled

Bit 1 CC1IE: Capture/Compare 1 interrupt enable

0: CC1 Interrupt disabled

1: CC1 Interrupt enabled

Bit 0 UIE: Update interrupt enable

0: Update Interrupt disabled

1: Update Interrupt enabled

654

3210

BIF

TIF

Reserved

CC2IF

CC1IF

UIF

rc_w0

Bit 7 BIF: Break interrupt flag

This flag is set by hardware as soon as the break input goes active. It can be cleared by software if

the break input is not active.

0: No break event occurred.

1: An active level has been detected on the break input.

Bit 6 TIF: Trigger interrupt flag

This flag is set by hardware on trigger event (active edge detected on TRGI signal, both edges in

case gated mode is selected). It is cleared by software.

0: No trigger event occurred.

1: Trigger interrupt pending.

Bits 5:3 Reserved

Bit 2 CC2IF: Capture/Compare 2 interrupt flag

Refer to CC1IF description

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