UM0851 datasheet(87/245 Pages) STMICROELECTRONICS

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UM0851

Communication device drivers

Doc ID 16604 Rev 2

87/245

The SPI bus specifies four logic signals.

●

SCLK - serial clock (output from master)

●

MOSI - master output, slave input (output from master)

●

MISO - master input, slave output (output from slave)

●

SS - slave select (active low; output from master)

SPEAr600 has three SSP ARM PL022 controllers and SPEAr3xx has one SSP ARM PL022

controller. SSP controllers are connected through the APB bus and thus they work on the

APB clock. SSP frequency is configured by dividing APB frequency with a factor specified in

the controller configuration.

SPEAr support both master and slave sides for the following interfaces:

●

Motorola SPI - compatible interface

●

Texas instruments synchronous serial interface

●

National Semiconductor Microwire interface

In SPEAr3xx, although four chip select lines are available, only one at a time can be

operational. The selection of the active one is done using the two GPIO lines 6 and 7. The

FSSOUT of SPI controller is multiplexed to the external CSx according to the following table.

4.6.2

Software overview

The SPI framework present in Linux supports only the master side of the Motorola SPI

interface. User applications can use the interface of the protocol drivers present in Linux.

Protocol drivers use the standard call provided by the SPI framework present in Linux. The

SPI controller driver provides interface to the SPI Framework for accessing the SPI

controller. The SPI controller transfers data through the SPI slave devices/memories

connected to it according to the configuration provided by the SPI controller driver. The

following figure presents the SPI software system architecture:

Table 29.

Section of active CSx signal by GPIO7 and GPIO6

GPIO[7]

GPIO[6]

CSx

CS1

CS2

CS3

CS4

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