LTC1153_15 datasheet(6/16 Pages) LINER

6 / 16 page

LTC1153

PI FU CTIO S

Drain Sense Pin

The drain sense pin is compared against the supply pin

voltage. If the voltage at this pin is more than 100mV

below the supply pin, the input latch will trip and the

MOSFET switch will be turned off.

This pin is also a high impedance CMOS gate with ESD

protection and therefore should not be forced beyond the

power supply rails.

Some loads, such as large supply capacitor, lamps, or

motors require high inrush currents. An RC time is added

between the sense resistor and the drain sense pin to

ensure that the drain sense circuitry does not false trigger

during start-up. This trip delay can be set from a few

microseconds to many seconds. However, very long de-

lays may put the MOSFET switch in risk of being destroyed

by a short-circuit condition. (see Applications Information

Section).

Status Pin

The status pin is an open-drain output which is driven low

whenever the breaker is tripped. A 51k pull-up resistor

should be connected between this output and a logic

supply. The status pins of multiple LTC1153s can be OR’d

together if independent fault sensing is not required. No

connection is required to this pin when not in use.

DAGRA

BLOCK

GATE CHARGE

AND DISCHARGE

CONTROL LOGIC

SHUTDOWN

TTL-TO-CMOS

CONVERTER

OSCILLATOR

AND CHARGE

PUMP

FAST/SLOW

GATE CHARGE

LOGIC

FAULT DETECTION

AND STATUS

OUTPUT DRIVER

100mV

REFERENCE

COMP

ANALOG SECTION

INPUT

LATCH

GATE

SHUTDOWN

DRAIN

SENSE

ONE

SHOT

TTL-TO-CMOS

CONVERTER

VOLTAGE

REGULATORS

ANALOG

DIGITAL

GND

LOW STANDBY

CURRENT

REGULATOR

AUTO-RESET

TIMER

INPUT

TIMER

CAP

STATUS

µs

DELAY

LTC1153 • BD01

LTC1153 Scheda tecnica(PDF) 6 Page - Linear Technology

LTC1153 Scheda tecnica(HTML) 6 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Scheda tecnica Scarica

Link URL