AN4206 datasheet(14/34 Pages) STMICROELECTRONICS

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Power supplies

AN4206

14/34

DocID023944 Rev 4

Power reset

A power reset is generated when one of the following events occurs:

Power-on/power-down reset (POR/PDR reset)

When exiting Standby mode

Backup domain reset

The backup domain has two specific resets that affect only the backup domain. A backup

domain reset is generated when one of the following events occurs:

Software reset, triggered by setting the BDRST bit in the Backup domain control

VDD or VBAT power on, if both supplies have previously been powered off.

1.2.2

Power on reset (POR) / power down reset (PDR)

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits

which are always active and ensure proper operation above a threshold of 2 V.

The device remains in Reset mode when the monitored supply voltage is below a specified

threshold, VPOR/PDR, without the need for an external reset circuit.



The POR monitors only the VDD supply voltage. During the startup phase VDDA must

arrive first and be greater than or equal to VDD.



The PDR monitors both the VDD and VDDA supply voltages. However, the VDDA power

supply supervisor can be disabled (by programming a dedicated option bit

VDDA_MONITOR) to reduce the power consumption if the application design ensures that

VDDA is higher than or equal to VDD.

For more details on the power on / power down reset threshold, refer to the electrical

characteristics section in the datasheet.

Figure 7. Power on reset/power down reset waveform

AN4206 Scheda tecnica(PDF) 14 Page - STMicroelectronics