DocID024781 Rev 1

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AN4308

Application dependent CTLx controlling options

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Application dependent CTLx controlling options

2.1

CTLx pins controlled by GPIO from embedded controller

In this case, full remote wakeup in the S3 can be achieved by not toggling CTL1 when the

NB enters the S3 state. Thus only 2 GPIOs are needed with the CTL1 and CTL2 tied

together. The CTL3 pin can be user-configurable (BIOS, etc.) to enable/disable the charging

feature.

2.2

New Intel chipset such as Chief River, X79 (Padsburg), NM10 (Pinetrail) have sleep signals

linked to NB power states, described as the SLP_Sx:

Table 3. SLP_Sx truth table

Table 2. GPIO control truth table

Power state

CTL1 = CTL2

CTL3

Mode

S0/S3

1

0

SDP

1. No charging of full-speed/high-speed PDs in the S3, but full remote wakeup support

1

1

CDP

S4/S5

0

1

DCP auto

Any, typically S4/S5

0

0

OFF

Power state

SLP_S3

SLP_S4

SLP_S5

S0

1

1

1

S3

0

1

1

S4

0

0

1

S5

0

0

0