UPD75004 datasheet(21/66 Pages) NEC

21 / 66 page

µPD75004, 75006, 75008

5.2

CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and

system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

• 0.95

µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)

• 122

µs (subsystem clock: 32.768 kHz)

*: instruction execution.

Remarks 1: fX = Main system clock frequency

2: fXT = Subsystem clock frequency

Φ= CPU clock

4: PCC: Processor clock control register

5: SCC: System clock control register

6: One clock cysle (tCY) of

Φ is one machine cycle of an instruction. For tCY, refer to AC

characteristics in 10. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

XT1

XT2

f XT

f X

Watch timer

Subsystem

clock

oscillator

Main system

clock

oscillator

1/2 1/16

1/8 to 1/4096

Frequency divider

· Basic interval timer (BT)

· Timer/event counter

· Serial interface

· Watch timer

· INT0 noise rejecter circuit

· Clock output circuit

WM.3

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

HALT*

STOP*

PCC2, PCC3

clear signal

STOP F/F

HALT F/F

Oscillator

disable

signal

Frequency

divider

1/4

· CPU

· INT0 noise

rejecter circuit

· Clock output

circuit

Wait release

signal from BT

RESET signal

Standby release

signal from interrupt

control circuit

UPD75004 Scheda tecnica(PDF) 21 Page - NEC

UPD75004 Scheda tecnica(HTML) 21 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Scheda tecnica Scarica

Link URL