LT1394CS8 datasheet(3/16 Pages) LINER

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LT1394

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VOL

Output Voltage Swing Low

IOUT = – 4mA

0.3

0.5

IOUT = – 10mA

0.4

I+

Positive Supply Current

8.5

10.0

I–

Negative Supply Current

1.2

2.2

2.5

VIH

LATCH Pin High Input Voltage

VIL

LATCH Pin Low Input Voltage

0.8

IIL

LATCH Pin Current

VLATCH = 0V

–4

– 10

µA

tPD

Propagation Delay (Note 7)

∆VIN = 100mV, VOD = 5mV

∆tPD

Differential Propagation Delay (Note 7)

∆VIN = 100mV, VOD = 5mV

0.5

2.2

tLPD

Latch Propagation Delay (Note 8)

tSU

Latch Setup Time (Note 8)

– 0.4

Latch Hold Time (Note 8)

2ns

tPW(D)

Minimum Disable Pulse Width

3ns

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: This parameter is guaranteed to meet specified perforamnce

through design and characterization. It has not been tested.

Note 3: The LT1394CMS8 and LT1394CS8 are guaranteed to meet

specified performance from 0

°C to 70°C and are designed, characterized

and expected to meet these extended temperature limits, but are not tested

at – 40

°C and 85°C. The LT1394IS8 is guaranteed to meet the extended

temperature limits.

Note 4: Input offset voltage (VOS) is defined as the average of the two

voltages measured by forcing first one output, then the other to 1.4V.

Note 5: Input bias current (IB) is defined as the average of the two input

currents.

Note 6: Input voltage range is guaranteed in part by CMRR testing and in

part by design and characterization.

Note 7: tPD and ∆tPD cannot be measured in automatic handling

equipment with low values of overdrive. The LT1394 is 100% tested with a

100mV step and 20mV overdrive. Correlation tests have shown that tPD

and

∆tPD limits can be guaranteed with this test, if additional DC tests are

performed to guarantee that all internal bias conditions are correct.

Propagation delay (tPD) is measured with the overdrive added to the actual

VOS. Differential propagation delay is defined as:

∆tPD = tPDLH – tPDHL

Note 8: Latch propagation delay (tLPD) is the delay time for the output to

respond when the LATCH pin is deasserted. Latch setup time (tSU) is the

interval in which the input signal must remain stable prior to asserting the

latch signal. Latch hold time (tH) is the interval after the latch is asserted in

which the input signal must remain stable.

The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.

V+ = 5V, V– = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.

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