5

LT1431

PI FU CTIO S

COLL (Pin 1): Open collector of the output transistor. The

maximum pin voltage is 26V. The saturation voltage at

100mA is approximately 1V.

COMP (Pin 2): Base of the driver for the output transistor.

This pin allows additional compensation for complex

feedback systems and shutdown of the regulator. It must

be left open if unused.

maximum input voltage is 36V and the minimum to

typically 0.6mA.

that guarantees 1% accuracy of operation as a 5V shunt

regulator with no external trim. The pin is tied to COLL for

self-contained 5V operation. It may be left open if unused.

See note on parasitic diodes below.

GND-S (Pin 5): Ground reference for the on-chip resistive

divider and shunt regulator circuitry except for the output

transistor. This pin allows external current limit of the

output transistor with one resistor between GND-F (force)

and GND-S (sense).

GND-F (Pin 6): Emitter of the output transistor and sub-

strate connection for the die.

contained 5V operation. It may be left open if unused.

REF (Pin 8): Control pin of the shunt regulator with a 2.5V

tion circuits that must not be activated on a continuous

basis. Therefore, the absolute maximum DC voltage on

these pins is 6V, well beyond the normal operating condi-

tions.

As with all bipolar ICs, the LT1431 contains parasitic

diodes which must not be forward biased or else anoma-

lous behavior will result. Pin conditions to be avoided are

voltage (except for GND-S).

The following pin definitions apply to the Z package.

together.

ANODE (Pin 2): Corresponds to GND-S and GND-F tied

together.

REF (Pin 3): Corresponds to REF.

I

DAGRA

BLOCK

LT1431 • BD01

COMP

V

+

GND-FORCE

GND-SENSE

REF

2.5V

+

–

gm =

4mA/V

5k

COLLECTOR

8

7

5

43

2

1

6

5k