UPD754202 datasheet(49/66 Pages) NEC

49 / 66 page

µPD754202, 754202(A)

0.5

Supply voltage VDD [V]

(During system clock operation)

tCY vs VDD

Operation

guaranteed range

AC Characteristics (TA = –40 to +85

°C, VDD = 1.8 to 6.0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle timeNote 1

tCY

When system

2.7 V

≤ VDD ≤ 6.0 V

0.67

64.0

µs

(Minimum instruction execution

clock is used

time = 1 machine cycle)

1.8 V

≤ VDD < 2.7 V

0.95

64.0

µs

Interrupt input high- and

tINTH, tINTL

INT0

IM02 = 0

Note 2

µs

low-level widths

IM02 = 1

µs

KR4-KR7

µs

RESET low-level width

tRSL

µs

Notes 1.

The CPU clock (

Φ) cycle time (minimum

instruction execution time) is determined

by the oscillation frequency of the con-

nected resonator (and external clock) and

the processor clock control register (PCC).

The figure on the right shows the cycle

time tCY characteristics against the supply

voltage VDD when the system clock is used.

2tCY or 128/fx depending on the setting of

the interrupt mode register (IM0).

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