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LTC3853

3853fc

For more information www.linear.com/LTC3853

Figure 10. Relationship Between Oscillator

Frequency and Voltage at the FREQ/PLLFLTR Pin

Phase-Locked Loop and Frequency Synchronization

The LTC3853 has a phase-locked loop (PLL) comprised of

an internal voltage-controlled oscillator (VCO) and a phase

detector. This allows the turn-on of the top MOSFET of

controller 1 to be locked to the rising edge of an external

clock signal applied to the MODE/PLLIN pin. The phase

detector is an edge sensitive digital type that provides

zero degrees phase shift between the external and internal

oscillators. This type of phase detector does not exhibit

false lock to harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the external

filter network connected to the FREQ/PLLFLTR pin. The

relationship between the voltage on the FREQ/PLLFLTR

pin and operating frequency is shown in Figure 10 and

specified in the Electrical Characteristics table. Note that

the LTC3853 can only be synchronized to an external

clock whose frequency is within range of the LTC3853’s

internal VCO. This is guaranteed to be between 250kHz and

750kHz. A simplified block diagram is shown in Figure 11.

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC,oriftheexternalclock’sphase

lags the internal oscillator, then current is sourced from

the phase detector output, pulling up the FREQ/PLLFLTR

pin. When the external clock frequency is less than fOSC,

or if the external clock’s phase leads the internal oscilla-

tor, current is sunk, pulling down the FREQ/PLLFLTR pin.

The voltage on the FREQ/PLLFLTR pin is adjusted until the

phase and frequency of the internal and external oscilla-

tors are identical. At the stable operating point, the phase

detector output is high impedance and the filter capacitor,

CLP, holds the voltage.

The loop filter components, CLP and RLP, smooth out

the current pulses from the phase detector and provide a

stable input to the voltage-controlled oscillator. The filter

components CLP and RLP determine how fast the loop

acquires lock. Typically RLP = 10k and CLP is 2200pF to

0.01µF.

Typically, the external clock (on MODE/PLLIN pin)

input high threshold is 1.6V, while the input low threshold

is 1V.

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest time duration

that the LTC3853 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

tON(MIN) <

VOUT

VIN(f)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

Figure 11. Phase-Locked Loop Block Diagram

APPLICATIONS INFORMATION

FREQ/PLLFLTR PIN VOLTAGE (V)

0.5

1.5

3853 F10

2.5

300

400

500

800

700

200

600

DIGITAL

PHASE/

FREQUENCY

DETECTOR

VCO

2.4V

RLP

CLP

3853 F11

FREQ/

PLLFLTR

EXTERNAL

OSCILLATOR

MODE/

PLLIN

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