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MAX1069 Scheda tecnica(PDF) 4 Page - Maxim Integrated Products

Il numero della parte MAX1069
Spiegazioni elettronici  58.6ksps, 14-Bit, 2-Wire Serial ADC
PDF  20 Pages
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Produttore elettronici  MAXIM [Maxim Integrated Products]
Homepage  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1069 Scheda tecnica(HTML) 4 Page - Maxim Integrated Products

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58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external ref-
erence applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.7
5.5
V
fSAMPLE = 58.6ksps
1.8
2.5
fSAMPLE = 10ksps
0.7
mA
fSAMPLE = 1ksps
40
Internal reference
(powered down
between conversions,
R/W = 0)
Shutdown
0.4
5.0
µA
fSAMPLE = 58.6ksps
1.8
2.5
fSAMPLE = 10ksps
1.4
mA
fSAMPLE = 1ksps
1.1
mA
Internal reference
(always on, R/W = 1)
Shutdown
0.4
5
µA
fSAMPLE = 58.6ksps
0.90
1.8
fSAMPLE = 10ksps
0.36
mA
fSAMPLE = 1ksps
40
Analog Supply Current
IAVDD
External reference
(REFADJ = AVDD)
Shutdown
0.4
5
µA
fSAMPLE = 58.6ksps
260
400
fSAMPLE = 10ksps
65
fSAMPLE = 1ksps
6
Digital Supply Current
IDVDD
Shutdown
0.2
5
µA
Power-Supply Rejection Ratio
PSRR
AVDD = 5V ±5%, full-scale input (Note 8)
2
6
LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time for Start Condition
tHD,STA
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated
START Condition (Sr)
tSU,STA
0.6
µs
Data Hold Time
tHD,DAT
(Note 9)
0
900
ns
Data Setup Time
tSU,DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Note 10)
20 +
0.1CB
300
ns
Fall Time of SDA Transmitting
tF
(Note 10)
20 +
0.1CB
300
ns
Setup Time for STOP Condition
tSU,STO
0.6
µs
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns



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