Low-Cost, 2-Channel, ±14-Bit Serial ADCs

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13

CS

SCLK

MSB

LSB

DIN

DOUT

BUSY

POL

OFL

MSB

DO

END OF

CONVERSION

START OF

CONVERSION

Figure 6. Detailed Serial-Interface Timing

The ADC serial interface operates with just SCLK, DIN,

and DOUT (allow sufficient time for the conversion to

complete between read/write operations). Achieve con-

tinuous operation by connecting BUSY to an uncommit-

ted µP I/O or interrupt, to signal the processor when the

conversion results are ready. Figures 8a and 8b show

the timing for SPI/MICROWIRE and QSPI operation.

The fully static 16-bit I/O register allows infinite time

between the two 8-bit read/write operations necessary

to obtain the full 16 bits of data with SPI and

MICROWIRE. CS must remain low during the entire

two-byte transfer (Figure 8a). QSPI allows a full 16-bit

data transfer (Figure 8b).

Interfacing to the 80C32 Microcontroller Family

Figure 7c shows the general 80C32 connection to the

MAX110/MAX111 using Port 1. For a more detailed dis-

cussion, see the MAX110 evaluation kit manual.

I/O Shift Register

Serial data transfer is accomplished with a 16-bit fully

static shift register. The 16-bit control word shifted into

this register during a data-transfer operation controls

the ADC’s various functions. The MSB (NO-OP)

enables/disables transfer of the control word within the

ADC. A logic 1 causes the remaining 15 bits in the con-

trol word to be transferred from the I/O register into the

control register when CS goes high, updating the

ADC’s configuration and starting a new conversion. If

I/O

SCK

MISO

MOSI

MASKABLE

INTERRUPT

SS

a. SPI/QSPI

+5V

µP

CS

SCLK

DOUT

DIN

BUSY

MAX110

MAX111

I/O

SK

SI

SO

MASKABLE

INTERRUPT or I/O

b. MICROWIRE

µP

CS

SCLK

DOUT

DIN

BUSY

P1.0

P1.1

P1.2

P1.3

P1.4

c. 80C51/80C32

µP

CS

SCLK

DIN

DOUT

BUSY

MAX110

MAX111

MAX110

MAX111

Figure 7. Common Serial-Interface Connections