Single-Chip, 8-Bit CCD Digitizer

with Clamp and 6-Bit PGA

_______________________________________________________________________________________

5

Programmable-Gain Amplifier

The PGA amplifies the differential video signal from the

CCD (at CCDIN). Gain is settable with the 6-bit con-

trol word from -2 to -10 in 64 steps, in increments of

-0.125. The PGA also provides for periodic DC restora-

tion of the capacitively coupled input.

As shown in Figure 2, the switched-capacitor amplifier’s

The 6-bit gain control word determines the number

of capacitors used. Thus the PGA gain is set from

-2 to -10.

verting input. This offsets the PGA output to be within

Clamp Circuit

As shown in Figure 2, the CCD output is connected to

the MAX1101 input (CCDIN) through an external

capacitor, which removes the potentially large DC

common-mode voltages from the input signal.

Whenever CLAMP is high, the CLAMP switch is closed

either once per pixel (sampling reset level) or less fre-

quently (such as for restoring optical black level once

per line), as required by the application.

VIDSAMP controls the sampling of the video signal

and offset nulling of the PGA. To null out the offset,

VIDSAMP causes switches S1 and S1P to close, plac-

ing the amplifier in a unity-gain configuration, as shown

in Figure 3a. This configuration causes the amplifier’s

offset voltage to be stored on CF. In the next portion of

the cycle, when VIDSAMP returns low, the S1 switches

are opened and S2 is closed (Figure 3b). This is the

standard inverting op-amp configuration. The only dif-

ference is that capacitors are used to set the gain, and

the amplifier’s offset voltage has been stored on these

capacitors and is thus canceled. The amplifier’s output

in Figure 4.

ADC

The ADC uses a recycling half-flash conversion tech-

nique in which a 4-bit flash ADC section achieves an

8-bit result in two steps (Figure 5). Using 15 compara-

tors, the flash ADC compares the unknown input

voltage to the reference ladder (using REF+ and REF-)

and provides the upper four data bits.

An internal digital-to-analog converter (DAC) uses the

four most significant bits (MSBs) to generate the analog

result from the first flash conversion and a residue volt-

age that is the difference between the unknown voltage

Figure 2. PGA Functional Diagram

S1

S2

S1P

S2

S1

CLAMP

CF

0.047

µF

REF-

REF-

REF+

REF+

TO

ADC

FROM

CCD

VIDSAMP

S1

S2

S1P

ON

ON

ON

OFF

OFF

OFF

* INTERNALLY GENERATED SIGNALS

*

*

*

REF-

REF+

REF-

REF-

(FROM DC

RESTORE)

Figure 3a. PGA Connection with VIDSAMP = Low

Figure 3b. PGA Connection with VIDSAMP = High