Direct-Conversion Tuner ICs for

Digital DBS Applications

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9

Pin Description

RF Ground. Connect directly to the ground plane.

GND

9, 11,

19, 24

Automatic Gain-Control Input. Bypass this pin with a 1000pF capacitor close to the pin, to minimize cou-

pling.

AGC

10

Q Channel Baseband Output

QOUT

13

Baseband +5V Supply. Bypass with a 10pF capacitor from this pin to pin 12 (GND), as close to the IC as

possible. Connect an additional 0.1µF capacitor in parallel with the 10pF capacitor (placement less critical).

14

Q Channel Offset-Correction Noninverting Input. Connect a 0.22µF (typ) capacitor between QDC and QDC.

This capacitor must be placed as close to the IC as possible (see

Layout Considerations section).

QDC

15

Ground (substrate)

GND

5

RF +5V Supply. Bypass with a 22pF capacitor from this pin to pin 9 (GND), as close to the IC as possible.

6

RF Noninverting Input. Couple through a 22pF capacitor directly to a 50

Ω signal source.

RFIN

7

RF Inverting Input. Connect to a 22pF series capacitor and a 51

Ω resistor to ground.

RFIN

8

RF +5V Supply. Bypass with a 22pF capacitor from this pin to pin 11 (GND), as close to the IC as possible.

4

Baseband Ground

GND

3, 12

PIN

I Channel Baseband Output

IOUT

2

Baseband +5V Supply. Bypass with a 10pF capacitor from this pin to pin 3 (GND), as close to the IC as

possible. Connect an additional 0.1µF capacitor in parallel with the 10pF capacitor (placement less critical).

1

FUNCTION

NAME

Q Channel Offset-Correction Inverting Input. Connect a 0.22µF (typ) capacitor between QDC and QDC. This

capacitor must be placed as close to the IC as possible (see

Layout Considerations section).

QDC

16

I Channel Offset-Correction Inverting Input. Connect a 0.22µF (typ) capacitor between IDC and IDC. This

capacitor must be placed as close to the IC as possible (see

Layout Considerations section).

IDC

17

I Channel Offset-Correction Noninverting Input. Connect a 0.22µF (typ) capacitor between IDC and IDC.

This capacitor must be placed as close to the IC as possible (see

Layout Considerations section).

IDC

18

RF +5V Supply. Bypass with a 10pF capacitor from this pin to pin 19 (GND) as close to the IC as possible.

20

Local-Oscillator Complementary Input Port (Figure 1)

LO

21

Local-Oscillator Input Port (Figure 1)

LO

22

RF +5V Supply. Bypass with a 10pF capacitor from this pin to pin 24 (GND) as close to the IC as possible.

23

Prescaler Ground. To disable the prescaler, leave this pin open.

PSGND

25

Prescaler Output. Drives CMOS load. Connect 2k

Ω from this pin to GND (if the prescaler is enabled).

PSOUT

26

Prescaler Modulus Control. Leave open when the prescaler is disabled.

MOD

27

Prescaler +5V Supply. Must be connected even if the prescaler is disabled. Bypass with a 1000pF

capacitor.

28