Multirange, Single +5V, 12-Bit DAS

with 12-Bit Bus Interface

12

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WR

CLK

CLK

WR

WR GOES HIGH WHEN CLK IS HIGH

WR GOES HIGH WHEN CLK IS LOW

ACQUISITION STARTS

ACQUISITION STARTS

CONVERSION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQUISITION ENDS

ACQMOD = "0"

ACQMOD = "0"

Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)

WR

CLK

CLK

WR

WR GOES HIGH WHEN CLK IS HIGH

WR GOES HIGH WHEN CLK IS LOW

ACQUISITION STARTS

ACQUISITION STARTS

CONVERSION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQUISITION ENDS

ACQMOD = "1"

ACQMOD = "1"

ACQMOD = "0"

ACQMOD = "0"

Figure 8b. External Clock and WR Timing (External Acquisition Mode)