SM34 Data Sheet #:

TM095

Page 13

Rev:

05 Date: 11/19/12

© Copyright 2012 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Register Descriptions and Operation

Chip_ID_low, 0x00 (R)

Bit 7 ~ Bit 0

LowbyteofchipID:0x12

Chip_ID_High, 0x01 (R)

Bit 7 ~ Bit 0

HighbyteofchipID:0x30

Chip_Revision, 0x02 (R)

Bit 7 ~ Bit 0

Chiprevisionnumber:0x06

Bandwidth_PBO, 0x03 (R/W)

Bit 7 ~ Bit 5

Bit 4

Bit 3 ~ Bit 0

Reserved

Reserved

BandwidthSelectioninHz:

0:Default

0000:0.025

0001:0.025

0010:0.025

0011:0.025

0100:0.025

0101:0.025

0110:0.049

0111:0.098(ResetDefault)

1000:0.20

1001:0.39

1010:0.78

1011-1111:1.6

BITS3-0selectthephaselockloopbandwidthinHertz.

Ctl_Mode, 0x04 (R/W)

Bit 7 ~ Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Default:0

8k_Out

BITSClock

HMRef:

Active

Reserved

Pulsewidth

Output

0:Registercontrol

Reference

control:

Frequency:

ofopmode/ref

Selection:

0:50%

1:1.544MHz

(Willalways

1:Manual

1:Controlledby

0:2.048MHz

be0)

0:Automatic

FR_Pulse_Width

(readonly)

Default:1

register

Default:0

Whenbit1isreset(automaticreferenceandmodeselection),Bits3-0oftheOp_Moderegisterbecomeread-

only.Thepower-updefaultforBit1=1formanualreferenceselectionanddefaultforBit4=0for50%dutycycleon

8k_Out.

Whenthedeviceisinslavemode,itwilllocktotheM/SREF,independentofthevalueswrittentoBITS3-0

oftheOp_moderegister.TheoperationalmodeandreferenceselectionwrittentoBits3-0whileinslavemodewill,

however,takeeffectwhenthedeviceismadethemaster.

Whenbit1oftheCtl_Moderegisterisreset(automaticreferenceandmodeselection)andthedeviceisinmas-

termode,BITS3-0oftheOp_Moderegisterbecomeread-only.