8x4 Video Crosspoint Switches with Buffers

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9

_______________Detailed Description

Analog Section

The MAX458/MAX459 video crosspoint switches consist

of a high-speed 32 (8x4) switch array with wide-band-

width line drivers (Figure 1). This design allows make-

before-break switching to reduce output noise and

glitches, but the inputs will not short together. It also pro-

vides high input impedance and low input capacitance,

so no input buffer amplifier is needed. However,

because different transistors provide gain depending on

the input selection, the DC offset voltage shifts slightly

when a new input is switched in. The change in offset

voltage is typically 3mV.

All output buffers will drive back-terminated 50

Ω, 75Ω,

or higher impedance lines with up to 100pF capaci-

tance. The amplifier outputs can be disabled, which is

useful for creating large arrays. When disabled, the

MAX458 presents an output impedance of approxi-

mately 1M

Ω. The MAX459 disabled output impedance

is 1k

Ω (to ground), due to the internal feedback resis-

tors used to achieve the gain of two.

During power-on, if

–

C

—

S

–

and

–

U

—

P

—

D

—

A

—

T

—

E

–

are held high, all

output amplifiers are disabled. In a large array, this

feature prevents two ON paralleled amplifiers from dis-

torting each other’s signals. The amplifiers can be pro-

grammed to come up in any state simultaneously at any

time after power-on. See the

Creating Large Arrays

section.

Digital Section—Parallel Mode

The MAX458/MAX459 have two register banks—an

input register and a switch register (Figure 2). Each of

these registers is either latched (when the control input

is high) or transparent (when the control input is low).

The input register is controlled by

–

W

—

R

–

and

–

C

—

E

–

and is

selected by the decode of A0 and A1. If both

–

W

—

R

–

and

–

C

—

E

–

are low, the input register selected by A0 and A1 is

transparent, and the state of D0–D3 is presented to the

switch register. The other three input registers remain

latched. If D0–D3 change before

–

U

—

P

—

D

—

A

—

T

—

E

–

is asserted

(goes low), the new data (the changed D0–D3) will then

be latched in the switch register. If

–

W

—

R

–

or

–

C

—

E

–

is high, all

input registers are latched and their data is presented

Table 1. Amplifier Selection

Table 2. Input Selection

Table 3. Writing Data

H

H

L

L

H

L

–

U

—

P

—

D

—

A

—

T

—

E

–

L

L

H

X

H

X

X

H

X

H

L

L

All switch registers and selected input regis-

ter are transparent. Selected amplifier (cho-

sen by state of A0, A1) reflects input data.

Other amplifiers reflect data that had been

latched into the input registers previously.

Input register of selected amplifier is trans-

parent. Switch registers are latched. Other

input registers are latched.

Data in input registers passes through

switch registers. Output reflects data in

input registers.

Device not selected or is operating in seri-

al mode. Both registers are latched.

FUNCTION

–

W

—

R

–

–

C

—

E

–

X

X

H

X

Disable output amplifier

selected by A0, A1.

H

H

L

L

L

H

L

H

L

L

L

L

H

H

H

H

7

6

5

4

H

H

L

L

L

H

L

H

D0

D1

L

L

L

L

L

L

L

L

3

2

1

0

Input Channel Selected

D2

D3

H

H

L

L

L

H

L

H

3

2

1

0

Output Amplifier Selected

A0

A1

MAX458

MAX459

CS

SCLK

WR

CE

A0

A1

D0

D1

D2

D3

DOUT

SHDN

DIN

UPDATE

WRITE

AMPLIFIER SELECT A0

CHIP ENABLE (SELECT)

AMPLIFIER SELECT A1

DATA BIT D0

DATA BIT D1

DATA BIT D2

SHUTDOWN

DATA BIT D3

40

39

37

36

26

25

24

23

22

19

1

20

21

38

UPDATE

Pin numbers apply to DIP package.

Figure 3. Parallel Connection (only logic pins shown)