Quad/Octal, 2-Wire Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________________________________________________________________________________

9

______________________________________________________________Pin Description

SCL

SDA

START CONDITION

STOP CONDITION

REPEATED START CONDITION

START CONDITION

Figure 1. 2-Wire Serial-Interface Timing Diagram

DIP

SO/SSOP

DIP/SO

SSOP

PIN

MAX521

NAME

MAX520

7

8

9

10

11

4

—

5

6

3

2

1

8

10

11

12

13

4

7, 9, 16, 20

5

6

3

2

1

12

13

14

15

14

15

17

18

16

19

17

18

19

20

21

22

23

24

Serial Clock Input

SCL

7

Serial Data Input

SDA

8

DAC4 Voltage Output

OUT4

—

DAC5 Voltage Output

OUT5

—

DAC6 Voltage Output

OUT6

—

Reference Voltage Input for DAC0

REF0

4

No Connect—not internally connected

N.C.

—

Digital Ground

DGND

6

Analog Ground

AGND

5

Reference Voltage Input for DAC1

REF1

3

DAC0 Voltage Output

OUT0

2

DAC1 Voltage Output

OUT1

1

9

10

—

—

—

5

4, 7, 14, 17

8

6

3

2

1

DAC7 Voltage Output

OUT7

—

Address Input 0; sets IC’s slave address

AD0

9

Address Input 1; sets IC’s slave address

AD1

10

Power Supply, +5V

12

—

11

12

15

Reference Voltage Input for DACs 4, 5, 6, and 7

REF4

—

—

Reference Voltage Input for DAC3

REF3

13

Reference Voltage Input for DAC2

REF2

14

DAC3 Voltage Output

OUT3

15

DAC2 Voltage Output

OUT2

16

16

18

19

20

FUNCTION

—

—

Address Input 2; sets IC’s slave address

AD2

11

13