IRMCK341

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TABLE OF FIGURES

Figure 1. Typical Application Block Diagram Using IRMCK341.....................................................5

Figure 2. IRMCK341 Internal Block Diagram.................................................................................6

Figure 3. IRMCK341 Pin Configuration..........................................................................................8

Figure 4. Input/Output of IRMCK341 .............................................................................................9

Figure 5. Application Connection of IRMCK341 ..........................................................................13

Figure 6. Clock Frequency vs. Power Consumption....................................................................14

Figure 7 Crystal oscillator circuit..................................................................................................18

Figure 8 Voltage droop of sample and hold.................................................................................19

Figure 9 SYNC to SVPWM and A/D Conversion AC Timing .......................................................20

Figure 10 GATEKILL to SVPWM AC Timing ...............................................................................21

Figure 11 Interrupt AC Timing .....................................................................................................21

Figure 12 I2C AC Timing ..............................................................................................................22

Figure 13 SPI Write AC Timing....................................................................................................23

Figure 14 SPI Read AC Timing....................................................................................................24

Figure 15 UART AC Timing .........................................................................................................25

Figure 16 CAPTURE Input AC Timing.........................................................................................26

Figure 17 JTAG AC Timing..........................................................................................................27

Figure 18 OTP Programming Timing ...........................................................................................28

Figure 19 All digital I/O except motor PWM output.........................................................................29

Figure 20 RESET, GATEKILL I/O ..................................................................................................29

Figure 21 Analog input ...................................................................................................................30

Figure 22 Analog operational amplifier output and AREF I/O structure.......................................30

Figure 23 VPP programming pin

.................................................................................................30

Figure 24 VSS and AVSS pin structure..........................................................................................31

Figure 25 VDD1 and VDDCAP pin structure ..................................................................................31

Figure 26 XTAL0/XTAL1 pins structure .......................................................................................31