CMX608 datasheet(62/70 Pages) CMLMICRO

62 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

7.1.3.

Operating Characteristics

Using the recommended components in Figure 2 and Figure 3, and for the following conditions unless

otherwise specified:

Xtal Freq. = 12.0MHz ±100ppm, VDDPA = AVDD = IOVDD = 3.0V to 3.6V; VDD = 1.7V to 1.9V; Tamb = 25°C;

all gain settings are 0dB. Figures apply to CMX608, CMX618 and CMX638, unless otherwise stated.

Note: Parametric measurements in this section are subject to further characterisation.

Notes

Min.

Typ.

Max.

Units

DC Parameters

IDD Total powersaved

(ENABXTAL pin connected to VSS)

–

µA

IDD Digital

(after Reset, Xtal enabled)

1, 6, 9, 19

–

14.0

–

IDD IODigital

(after Reset, Xtal enabled)

1, 10, 19

–

0.5

–

IDD Digital

(CMX618/638 only)

1, 6, 9, 20

–

17.5

–

Operational Modes

IDD IODigital

(CMX618/638 only)

1, 10, 21

–

0.6

–

IDD Analogue PA

(CMX618/638 only)

1, 10, 21

–

0.7

–

IDD Analogue

(CMX618 only, Vocoder

encoding)

1, 10, 21

–

6.5

–

IDD Analogue

(CMX618 only, Vocoder

decoding)

1, 10, 21

–

2.8

–

IDD Digital

(CMX608/618 Vocoder encoding

enabled with clock throttling)

1, 6, 9

–

IDD Digital

(CMX608/618 Vocoder decoding

enabled with clock throttling)

1, 6, 9

–

20.0

–

IDD Digital

(CMX608/618 Vocoder encoding

enabled no clock throttling)

1, 9

–

IDD Digital

(CMX608/618 Vocoder decoding

enabled no clock throttling)

1, 9

–

IDD Analogue

(Full-duplex: CMX638 only)

1, 10, 21

–

IDD Digital

(Full-duplex: CMX638 only)

1, 9

–

Logic Inputs and Outputs

Input logic '1' level

80%

–

IOVDD

Input logic '0' level

–

20%

IOVDD

Input leakage current (Vin = 0 to IOVDD)

–

±5.0

µA

Input capacitance

–

Output logic '1' level

(IOH = 2mA)

90%

–

IOVDD

Output logic '0' level

(IOL = -5mA)

–

10%

IOVDD

"Off" state leakage current (IRQN or RDATA)

–

±5

µA

Analogue Outputs (CMX618/CMX638 only)

Differential output dc offset (OUT P

– OUT N)

–

±40

XTALin

Input logic '1' level

70%

–

IOVDD

Input logic '0' level

–

30%

IOVDD

Input current (Vin = 0 to IOVDD)

–

±40

µA

XTALout

Output logic '1' level

(IOH = 0.5mA)

90%

–

IOVDD

Output logic '0' level

(IOL = -1.2mA)

–

10%

IOVDD

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