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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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FX919B Scheda tecnica(PDF) 30 Page - CML Microcircuits |
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FX919B Scheda tecnica(HTML) 30 Page - CML Microcircuits |
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30 / 47 page  4-Level FSK Modem Data Pump FX919B © 1997 Consumer Microcircuits Limited 30 D/919B/1 1.6 Application Notes 1.6.1 Transmit Frame Examples The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are shown below: 1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQNEN and TXRXN bits of the Mode Register are '1', the RXEYE and PSAVE bits are '0' and the INVSYM bit is set appropriately. 2. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes to the Data Block Buffer and a T24S task to the Command Register. 3. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 4. Write 6 Frame Sync bytes to the Data Block Buffer and a T24S task to the Command Register. 5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 6. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register. 7. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 8. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register. 9. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 10. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 12. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits should be '1'. Note: The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass completely through the RRC filter. |
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