8

P/N:PM0676

REV. 0.2, MAR. 04, 2000

MX98715AEC-E

5.1.5 PCI BASE IO ADDRESS REGISTER ( PBIO ) ( Offset 13h-10h )

bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field.

bit 7 - 1 : not used, all 0 when read

bit 31 - 8 : Defines the address assignment mapping of MX98715AEC-E CSR registers.

5.1.6 PCI Base Memory Address Register ( PBMA ) ( Offset 17h-14h )

bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field.

bit 6 - 1 : not used, all 0 when read

bit 31 - 7 : Defines the address assignment mapping of MX98715AEC-E CSR registers.

5.1.7 PCI SUBSYSTEM ID REGISTER ( PSID ) ( Offset 2Ch-2Fh )

This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. Values in

this register are loaded directly from external serial EEPROM after system reset automatically. Word location 36h of

EEPROM is subsystem vendor ID and location 35h is sub-system ID.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Configuration Base Memory Address

Memory Spec Indicator

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Subsystem ID (31:16)

Subsystem Vendor ID (bit 15:0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Configuration Base IO Address

IO/Memory Spec Indicator