PIC16F628A-ISLASHP datasheet(47/168 Pages) MICROCHIP

47 / 168 page

 2002 Microchip Technology Inc.

Preliminary

DS40044A-page 45

PIC16F627A/628A/648A

6.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Read/Write capabilities

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module. Additional information is available in the

PICmicro™ Mid-Range MCU Family Reference Man-

ual, DS33023.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the TMR0 register value

will increment every instruction cycle (without pres-

caler). If the TMR0 register is written to, the increment

is inhibited for the following two cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

Counter mode is selected by setting the T0CS bit. In

this mode the TMR0 register value will increment either

on every rising or falling edge of pin RA4/T0CKI. The

incrementing edge is determined by the source edge

(T0SE) control bit (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are discussed in detail in Section 6.2.

The prescaler is shared between the Timer0 module

and the Watchdog Timer. The prescaler assignment is

controlled

software

the

control

bit

PSA

(OPTION<3>). Clearing the PSA bit will assign the

prescaler to Timer0. The prescaler is not readable or

writable. When the prescaler is assigned to the Timer0

module, prescale value of 1:2, 1:4,..., 1:256 are

selectable. Section 6.3 details the operation of the

prescaler.

6.1

Timer0 Interrupt

Timer0 interrupt is generated when the TMR0 register

timer/counter overflows from FFh to 00h. This overflow

sets the T0IF bit. The interrupt can be masked by clear-

ing

the

T0IE

bit

(INTCON<5>).

The

T0IF

bit

(INTCON<2>) must be cleared in software by the

Timer0 module interrupt service routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from SLEEP since the timer is shut

off during SLEEP.

6.2

Using Timer0 with External Clock

When an external clock input is used for Timer0, it must

meet

certain

requirements.

The

external

clock

requirement is due to internal phase clock (T

OSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

T0CKI

with

the

internal

phase

clocks

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-1). Therefore, it is necessary for T0CKI to be

high for at least 2T

OSC (and a small RC delay of 20 ns)

and low for at least 2T

OSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type

prescaler so that the prescaler output is symmetrical.

For

the

external

clock

meet

the

sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4T

OSC (and a small RC delay of 40 ns)

divided by the prescaler value. The only requirement

on T0CKI high and low time is that they do not violate

the minimum pulse width requirement of 10 ns. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device. See Table 17-9.

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