TC962 datasheet(5/12 Pages) MICROCHIP

5 / 12 page

 2002 Microchip Technology Inc.

DS21484B-page 5

TC962

3.0

APPLICATIONS INFORMATION

3.1

Theory of Operation

The TC962 is a capacitive pump (sometimes called a

switched capacitor circuit), where four MOSFET

switches control the charge and discharge of a

capacitor.

The functional block diagram shows how the switching

action works. SW1 and SW2 are turned on simulta-

neously, charging CP to the supply voltage, VIN. This

assumes that the on resistance of the MOSFETs in

series with the capacitor results in a charging time

(3 time constants) that is less than the on time provided

by the oscillator frequency as shown:

3 (RDS(ON) CP) < CP/(0.5 fOSC)

In the next cycle, SW1 and SW2 are turned off and after

a very short interval of all switches being off (this

prevents large currents from occurring due to cross

conduction), SW3 and SW4 are turned on. The charge

in CP is then transferred to CR, but with the polarity

inverted. In this way, a negative voltage is now derived.

An oscillator supplies pulses to a flip-flop that is then

fed to a set of level shifters. These level shifters then

drive each set of switches at one-half the oscillator

frequency.

The oscillator has two pins that control the frequency of

oscillation. Pin 7 can have a capacitor added that is

returned to ground. This will lower the frequency of the

oscillator by adding capacitance to the timing capacitor

internal to the TC962. Grounding pin 6 will turn on a

current source and double the frequency. This will

double the charge current going into the internal

capacitor, as well as any capacitor added to pin 7.

A zener diode has been added to the TC962 for use as

a reference in building external regulators. This zener

runs from pin 1 to ground.

3.2

Latch Up

All CMOS structures contain a parasitic SCR. Care

must be taken to prevent any input from going above or

below the supply rail, or latch up will occur. The result

of latch up is an effective short between VDD and VSS.

Unless the power supply input has a current limit, this

latch up phenomena will result in damage to the device.

(See AN763 Latch-up Protection of CMOS ICs.)

FIGURE 3-1:

TEST CIRCUIT

FIGURE 3-2:

TYPICAL APPLICATIONS

TC962

690

µF

COSC

VOUT

(–5V)

µF

(+5V)

TC962

CP2

CP1

CR1

µF

V+

µF

VOUT = –V+

VD1

VD2

VOUT =

µF

Combined Negative Converter and Positive Multiplier

µF

VOUT =

Split V+ In Half

TC962

Positive Voltage Multiplier

Lowering Output Resistance by Paralleling Devices

2V –2VD

TC962

µF

VOUT =

VD2

VD1

V+

2V –2VD

CP1

µF

CP2

µF

TC962

V+

VOUT

µF

V+

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