FC(SD)

OSC

LM2662 (LM2663)

LV

V+

CAP+

OUT

GND

OSCILLATOR

Switch Array

Switch Drivers

CAP-

LM2662, LM2663

SNVS002E – JANUARY 1999 – REVISED OCTOBER 2014

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8 Detailed Description

8.1 Overview

The LM2662/LM2663 contains four large CMOS switches which are switched in a sequence to invert the input

supply voltage. Energy transfer and storage are provided by external capacitors. Figure 16 illustrates the voltage

switches, and no ESR in the capacitors. In reality, the charge transfer efficiency depends on the switching

frequency, the on-resistance of the switches, and the ESR of the capacitors.

Figure 16. Voltage Inverting Principle

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Changing Oscillator Frequency

For the LM2662, the internal oscillator frequency can be selected using the Frequency Control (FC) pin. When

FC is open, the oscillator frequency is 20 kHz; when FC is connected to V+, the frequency increases to 150 kHz.

A higher oscillator frequency allows smaller capacitors to be used for equivalent output resistance and ripple, but

increases the typical supply current from 0.3 mA to 1.3 mA.

The oscillator frequency can be lowered by adding an external capacitor between OSC and GND (See typical

performance characteristics). Also, in the inverter mode, an external clock that swings within 100 mV of V+ and

GND can be used to drive OSC. Any CMOS logic gate is suitable for driving OSC. LV must be grounded when

driving OSC. The maximum external clock frequency is limited to 150 kHz.

The switching frequency of the converter (also called the charge pump frequency) is half of the oscillator

frequency.

NOTE

OSC cannot be driven by an external clock in the voltage-doubling mode.

10

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