ML4826 datasheet(10/16 Pages) MICRO-LINEAR

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ML4826

FUNCTIONAL DESCRIPTION (Continued)

PFC RAMP (RAMP1)

The intersection of RAMP1 and the boost current error

amplifier output controls the PFC pulse width. RAMP1 can

be generated in a similar fashion to the RTCT ramp.

The current error amplifier maximum output voltage has a

minimum of 6V. The peak value of RAMP1 should not

exceed that voltage. Assuming a maximum voltage of 5V

for RAMP1, Equation 6 describes the RAMP1 time. With a

100kHz PFC frequency, the resistor tied to VREF, and a

150pF capacitor, Equation 7 solves for the RAMP1 resistor.

RAMP

REF

RAMP

=×













=×

–

(6)

RAMP

1 1 150

Ω

(7)

VREF

ML4826

RAMP1

150pF

60k

Ω

Figure 3.

PMW SECTION

Pulse Width Modulator

The PWM section of the ML4826 is straightforward, but

there are several points which should be noted. Foremost

among these is its inherent synchronization to the PFC

section of the device, from which it also derives its basic

timing (at the PFC frequency in the ML4826-1, and at

twice the PFC frequency in the ML4826-2). The PWM is

capable of current-mode or voltage mode operation. In

current-mode applications, the PWM ramp (RAMP2) is

usually derived directly from a current sensing resistor or

current transformer in the primary of the output stage, and

is thereby representative of the current flowing in the

converter’s output stage. DC ILIMIT, which provides cycle-

by-cycle current limiting, is typically connected to RAMP

2 in such applications. For voltage-mode operation or

certain specialized applications, RAMP2 can be

connected to a separate RC timing network to generate a

voltage ramp against which VDC will be compared. Under

these conditions, the use of voltage feedforward from the

PFC buss can assist in line regulation accuracy and

response. As in current mode operation, the DC ILIMIT

input would be used for output stage overcurrent

protection.

No voltage error amplifier is included in the PWM stage of

the ML4826, as this function is generally performed on the

output side of the PWM’s isolation boundary. To facilitate

the design of optocoupler feedback circuitry, an offset has

been built into the PWM’s RAMP2 input which allows

VDC to command a zero percent duty cycle for input

voltages below 1.5V.

PWM Current Limit

The DC ILIMIT pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1V, the output of the PWM

will be disabled until the output flip-flop is reset by the

clock pulse at the start of the next PWM power cycle.

VIN OK Comparator

The VIN OK comparator monitors the DC output of the PFC

and inhibits the PWM if this voltage on VFB is less than its

nominal 2.5V. Once this voltage reaches 2.5V, which

corresponds to the PFC output capacitor being charged to

its rated boost voltage, the soft-start commences.

RAMP2

The RAMP2 input is compared to the feedback voltage

(VDC) to set the PWM pulse width. In voltage mode it can

be generated using the same method used for the RTCT

input. In current mode the primary current sense and

slope compensation are fed into the RAMP2 input.

Peak current mode control with duty cycles greater than

50% requires slope compensation for stability. Figure 4

displays the method used for the required slope

compensation. The example shown adds the slope

compensation signal to the current sense signal.

Alternatively, the slope compensation signal can also be

subtracted form the feedback signal (VDC).

In setting up the slope compensation first determine the

down slope in the output inductor current. To determine

the actual signal required at the RAMP2 input, reflect 1/2

of the inductor downslope through the main transformer,

current sense transformer to the ramp input.

Internal to the IC is a 1.5V offset in series with the RAMP2

input. In the example show the positive input to the PWM

comparator is developed from VREF (7.5V), this limits the

RAMP2 input (current sense and slope compensation) to 6

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