ML6440 datasheet(10/18 Pages) MICRO-LINEAR

10 / 18 page

ML6440

to the video content of the last 60+ lines (frames) of video

—a frame weighing function— to determine the best

filtering approach of the current video content. Finally, 1

of 7 thresholds can be chosen to adjust either real-time

(automatically) by the ML6440 itself or fixed manually by

design. An internal 12-bit analysis is used for the filtering

algorithm. An additional fader circuit is included to

"smooth" the transitions between comb and notch filtering.

In NTSC, every other line of chroma is inverted while

there are no changes in luma (assuming there is no change

in color between adjacent lines). This permits data to be

added from the first stored line of data with the third line

of active high-band video data, each with a scaling of

0.25, and add the second stored line of data with a scaling

of 0.50. The result contains no chroma, only luma

information. Subtracting this information from the high-

band signal yields only chroma information.

In PAL, each line of data rotates the phase of the chroma

by 90 degrees. Therefore, by adding the first line of stored

high-band information from the active third line, the

chroma is canceled, leaving only luma information. Once

again, this information is subtracted with the appropriate

amplitude scaling from the original highband information

to yield only chroma.

In bandsplit (notch) filtering and luma peaking, the digital

bandsplit filter is used as an alternate filter when the

SmartComb algorithm determines that the comb filter

output signal would be contaminated with cross chroma

artifacts. To maintain a reasonable amount of apparent

resolution in the luminance signal, luma peaking is

applied. This helps maintain image quality in the portion

of the video image where comb filtering would generate

artifacts.

The ML6440 SmartComb provides a real-time filtering

algorithm solution (automatic mode) for a wide variety of

video sources without the shortcomings of using fixed

thresholds (manual mode). The automatic threshold

tracking circuit responds quickly, adjusting itself in about

1/300th of a second (about 60 lines). The transition from

the comb to the digital bandsplit is made with a

continuous digital fader to prevents switching glitches.

The bandsplit-notch and comb filters were designed to

reduce color bar peak-to-peak dot edge crawl to <7.5%

for 75% color bars. Peak-to-peak cross color on the white

bar edge was designed to be <1% with 75% color bars.

SERIAL PROGRAM MODE

In Serial Program Mode, the comb filter can be controlled

with the serial interface. Control inputs may be clocked in

serially with S DATA and S CLK , when S/P is low. Serial

bus transfers require an 8-bit address followed by 8-bits of

data for the internal data register. The pattern is described

in Tables 1 through 5.

The serial bus control in the ML6440 has one level of

addressing followed by control register programming.

Figure 2 shows the physical waveforms generated in order

to address the ML6440. There are six basic parts of the

waveform:

1. Start indication: Clock Cycle 0

2. Device address shifted in: Clock Cycle 1 thru 8

3. Device address strobed /decoded: Clock Cycle 9

4. Data shifted in: Clock Cycle 10 thru 17

5. Data strobed to appropriate register: Clock Cycle 18

6. Stop indication: Clock Cycle 19

PARALLEL PROGRAM MODE

In Parallel Program Mode, the CI/DI[7:0] pins act as

programming pins for the internal 8-bit register (D[7:0])

such that CI7/DI7=D7, CI6/DI6=D6, ... CI0/DI0=D0. In

the parallel mode, the S/P serves as a rising edge-triggered

strobe pin for the internal registers of D[7:0]. When S/P

goes from low to high, data applied to the inputs (CI/

DI[7:0]), is loaded into the internal 8-bit register D[7:0]

directly. A transition on the S/P pin back to low will

reactivate the serial mode. If the S/P is held at a high, the

serial mode is inactive.

CONTROL REGISTER, D[7:0]

The internal register, D[7:0], controls the following

functions within the ML6440. Again, this register can be

programmed through either a serial or parallel interface.

The RST acts as a reset pin, forcing all the bits of the

FUNCTIONAL DESCRIPTION (Continued)

Figure 5: Reset Timing

POWER ON

AT LEAST 5µs HIGH

AT LEAST 1µs LOW

RST

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