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MT9V024 Scheda tecnica(PDF) 43 Page - ON Semiconductor |
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MT9V024 Scheda tecnica(HTML) 43 Page - ON Semiconductor |
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43 / 62 page ![]() MT9V024_DSRev. G Pub. 4/15 EN 42 ©Semiconductor Components Industries, LLC, 2015. MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor Feature Description Figure 33: Readout of 8 Pixels in Normal and Column Bin Output Mode Interlaced Readout The MT9V024 has two interlaced readout options. By setting R0x07[2:0] = 1, all the even- numbered rows are read out first, followed by a number of programmable field blanking rows (set by R0xBF[7:0]), then the odd-numbered rows, and finally the vertical blanking rows. By setting R0x07[2:0] = 2 only one field row is read out. Consequently, the number of rows read out is half what is set in the window height register. The row start register determines which field gets read out; if the row start register is even, then the even field is read out; if row start address is odd, then the odd field is read out. LINE_VALID Normal readout DOUT(9:0) PIXCLK DOUT(9:0) PIXCLK DOUT(9:0) PIXCLK D1 (9:0) D2 (9:0) D3 (9:0) D4 (9:0) D5 (9:0) D6 (9:0) D7 (9:0) D8 (9:0) LINE_VALID Column Bin 2 readout D1 (9:0) D3 (9:0) D5 (9:0) D7 (9:0) LINE_VALID Column Bin 4 readout DOUT(9:0) D1 (9:0) D5 (9:0) |
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