Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

SN74LS192 Scheda tecnica(PDF) 5 Page - ON Semiconductor

Il numero della parte SN74LS192
Spiegazioni elettronici  PRESETTABLE 4-BIT COUNTER
PDF  7 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

SN74LS192 Scheda tecnica(HTML) 5 Page - ON Semiconductor

  SN74LS192 Datasheet HTML 1Page - ON Semiconductor SN74LS192 Datasheet HTML 2Page - ON Semiconductor SN74LS192 Datasheet HTML 3Page - ON Semiconductor SN74LS192 Datasheet HTML 4Page - ON Semiconductor SN74LS192 Datasheet HTML 5Page - ON Semiconductor SN74LS192 Datasheet HTML 6Page - ON Semiconductor SN74LS192 Datasheet HTML 7Page - ON Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 5 / 7 page
background image
SN74LS192
http://onsemi.com
5
AC CHARACTERISTICS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
Maximum Clock Frequency
25
32
MHz
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
CPU Input to
TCU Output
17
18
26
24
ns
tPLH
tPHL
CPD Input to
TCD Output
16
15
24
24
ns
tPLH
tPHL
Clock to Q
27
30
38
47
ns
tPLH
tPHL
PL to Q
24
25
40
40
ns
tPHL
MR Input to Any Output
23
35
ns
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
Any Pulse Width
20
ns
VCC = 5.0 V
ts
Data Setup Time
20
ns
th
Data Hold Time
5.0
ns
trec
Recovery Time
40
ns
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to
the PL transition from LOW-to-HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following the
PL transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the
correct logic level may be released prior to the PL transition
from LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.



Html Pages

1 2 3 4 5 6 7


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com