continued

ValueRAM

Kingston.com

Document No. VALUERAM0530-001.A00 12/19/06 Page 5

Continued >>

Architecture:

Advanced Memory Buffer Pin Description:

Pin Name

Pin Description

Count

FB-DIMM Channel Signals

99

1

e

n

il

e

v

it

i

s

o

p

,t

u

p

n

I

k

c

o

l

C

m

e

t

s

y

S

K

C

S

SCK

1

e

n

il

e

v

it

a

g

e

n

,t

u

p

n

I

k

c

o

l

C

m

e

t

s

y

S

4

1

s

e

n

il

e

v

it

i

s

o

p

,

a

t

a

D

d

n

u

o

b

h

tr

o

N

y

r

a

m

ir

P

]

0

:

3

1

[

N

P

PN

4

1

s

e

n

il

e

v

it

a

g

e

n

,

a

t

a

D

d

n

u

o

b

h

tr

o

N

y

r

a

m

ir

P

]

0

:

3

1

[

0

1

s

e

n

il

e

v

it

i

s

o

p

,

a

t

a

D

d

n

u

o

b

h

t

u

o

S

y

r

a

m

ir

P

]

0

:

9

[

S

P

PS

0

1

s

e

n

il

e

v

it

a

g

e

n

,

a

t

a

D

d

n

u

o

b

h

t

u

o

S

y

r

a

m

ir

P

]

0

:

9

[

4

1

s

e

n

il

e

v

it

i

s

o

p

,

a

t

a

D

d

n

u

o

b

h

tr

o

N

y

r

a

d

n

o

c

e

S

]

0

:

3

1

[

N

S

SN

4

1

s

e

n

il

e

v

it

a

g

e

n

,

a

t

a

D

d

n

u

o

b

h

tr

o

N

y

r

a

d

n

o

c

e

S

]

0

:

3

1

[

0

1

s

e

n

il

e

v

it

i

s

o

p

,

a

t

a

D

d

n

u

o

b

h

t

u

o

S

y

r

a

d

n

o

c

e

S

]

0

:

9

[

S

S

SS

0

1

s

e

n

il

e

v

it

a

g

e

n

,

a

t

a

D

d

n

u

o

b

h

t

u

o

S

y

r

a

d

n

o

c

e

S

]

0

:

9

[

FBDRESTo an external precision cali

1

c

c

V

o

t

d

e

t

c

e

n

n

o

c

r

o

t

s

i

s

e

r

n

o

it

a

r

b

DDR2 Interface Signals

175

DQS[8:0]

Data Strobes, positive lines

9

DQS[8:0]

Data Strobes, negative lines

9

DQS[17:9]/DM[8:0]Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes.9

DQS

9

s

e

n

il

e

v

it

a

g

e

n

,)

y

l

n

o

M

A

R

D

4

x

(

s

e

b

o

rt

S

a

t

a

D

]

9

:

7

1

[

DQ[63:0]Data

64

CB[7:0]Checkbits

8

2

3

d

n

a

m

m

o

c

e

g

r

a

h

c

-

e

r

p

e

h

t

f

o

tr

a

p

s

i

0

1

A

.

s

e

s

s

e

r

d

d

A

B

]

0

:

5

1

[

A

,

A

]

0

:

5

1

[

A

BA[2:0]A, BA[2:0]BBank Addresses

6

RASA, RASBPart of command, with CAS, WE, and CS

2

.]

0

:

1

[

CASA, CASBPart of command, with RAS, WE, and CS

2

.]

0

:

1

[

WEA, WEBPart of command, with RAS, CAS, and CS

2

.]

0

:

1

[

ODTA, ODTB

On-die Termination Enable

2

CKE[1:0]A, CKE[1:0]BClock Enable (one per rank)

4

CS[1:0]A, CS[1:0]BChip Select (one per rank)

4

CLK[3:0]

CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out-

put disabled when not in use.

4

CLK[3:0]

Negative lines for CLK[3:0]

4

1

.

8

1

C

_

C

R

D

D

d

n

a

8

1

B

_

C

R

D

D

r

o

f

n

i

p

n

r

u

t

e

r

n

o

m

m

o

C

:

n

o

it

a

s

n

e

p

m

o

C

R

D

D

4

1

C

_

C

R

D

D

1

4

1

C

_

C

R

D

D

n

i

p

n

r

u

t

e

r

n

o

m

m

o

c

o

t

d

e

t

c

e

n

n

o

c

r

o

t

s

i

s

e

R

:

n

o

it

a

s

n

e

p

m

o

C

R

D

D

8

1

B

_

C

R

D

D

1

4

1

C

_

C

R

D

D

n

i

p

n

r

u

t

e

r

n

o

m

m

o

c

o

t

d

e

t

c

e

n

n

o

c

r

o

t

s

i

s

e

R

:

n

o

it

a

s

n

e

p

m

o

C

R

D

D

8

1

C

_

C

R

D

D

DDRC_B12

1

DDRC_C12

1