LC87F2K08A

No.A2275-2/24

 Ports

 I/O ports

Ports I/O direction can be designated in 1 bit units:

9 (P00 to P07, P30)

 Dedicated PPG ports

10 (PPGO, AMP1I, AMP2O, CMP1IA, CMP1IB, CMP2I,

CMP4I, CMP45I, CMP5I, CMP6I)

 Reset pin

1 (RES#)

 Dedicated on-chip debugger pin

1 (OWP0)

 Power pins

3 (VSS1, VSS2, VDD1)

 Timers

 Timer 0: 16-bit timer/counter with a capture register

Mode 0 :

8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)

2 channels

Mode 1 :

8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter

(with an 8-bit capture register)

Mode 2 :

16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)

Mode 3 :

16-bit counter (with a 16-bit capture register)

 Timer 1 : 16-bit timer/counter

Mode 0 :

8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler

Mode 2 :

16-bit timer/counter with an 8-bit prescaler

Mode 3 :

16-bit timer with an 8-bit prescaler

 Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)

 Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)

 Base timer

1) The clock is selectable from the system clock and timer 0 prescaler output.

2) Interrupts are programmable in 5 different time schemes.

 Serial interface

 SIO1: 8-bit asynchronous/synchronous serial interface

Mode 0 :

Synchronous 8-bit serial I/O (2-wire configuration, 2 to 512 Tcyc transfer clocks)

Mode 2 :

Bus mode 1 (start bit, 8 data bits, 2 to 512 Tcyc transfer clocks)

Mode 3 :

Bus mode 2 (start detect, 8 data bits, stop detect)

 UART

 Full duplex

 7/8/9 bit data bits selectable

 1 stop bit (2 bits in continuous data transmission)

 Built-in baudrate generator

 AD converter : 12 bits

5 channels

 12/8 bits AD converter resolution selectable

 Clock output function

 Can generate clock outputs with a frequency of

1

2

4

8

16

32

64

system clock.