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LC87F1HC4B Scheda tecnica(PDF) 26 Page - ON Semiconductor |
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LC87F1HC4B Scheda tecnica(HTML) 26 Page - ON Semiconductor |
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26 / 28 page ![]() LC87F1HC4B www.onsemi.com 26 Figure 5. External Filter Circuit for the Internal USB-dedicated PLL Circuit Figure 6. External Filter Circuit for Audio Interface (Used with Internal PLL Circuit) Figure 7. USB Port Peripheral Circuit When using the internal PLL circuit to generate the 48MHz clock for USB , it is necessary to connect a filter circuit such to the P34/UFILT pin such as that shown in the left Fig. Rd 0k Cd 2.2 F P34/UFILT + - 5pF 33 UHD- UHD+ 5pF 33 15k 15k It’s necessary to adjust the Circuit Constant of the USB Port Peripheral Circuit for each mounting board. To generate the master clock for the audio interface using the internal PLL circuit, it is necessary to connect a filter circuit to the P33/AFILT pin that is shown in the left Fig. Rd 150 Cd 4.7 F P33/AFILT + - Cp 1 F + - |
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