GP2021 datasheet(6/62 Pages) MITEL

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GP2021

Pin No

Signal Name

Type

Description ARM System Mode

Description Standard Interface

Mode

ABORT/ MICRO_CLK

Abort output to the microprocessor.

20MHz Clock output. Provides a

Generates a valid ARM Data Abort

20MHz clock with a 1:1

sequence, triggered by a rising edge

mark-to-space ratio

at MULTI_FN_IO if this function is

enabled.

DISCIO

I/O

Multi–purpose discrete input / output. After a GP2021 reset it is

configured as an input.

A22 / READ

Address input from the microprocessor.

Read input from the

A<22:20> are decoded to select the

microprocessor. In Intel mode

address space partitioning.

it is the active Low read strobe.

In Motorola mode it is the Read

(High)/Write (Low) select line.

A21 / NCS

Address input from the microprocessor.

GP2021 Chip Select input

A<22:20> are decoded to select the

(Active Low).

address space partitioning.

A20 / WREN

Address input from the microprocessor

Write–Read Strobe input from

A<22:20> are decoded to select the

the microprocessor. In Intel

address space partitioning.

mode it is the active Low write

strobe. In Motorola mode it is

the active High Write-Read

strobe.

38 – 45

A<9:2>

Address Inputs <9:2> from the microprocessor. These allow register

selection.

A1 / ALE_IP

Address input 1 from the

Address Latch Enable input

microprocessor. A<1:0> are decoded

from microprocessor (Active

to provide individual byte write

High)

selection via NW<3:0>.

A0 / NRESET_IP

Address input 0 from the

Reset input (Active Low).

microprocessor. A<1:0> are decoded

to provide individual byte write

selection via NW<3:0>.

48– 54,

D<0:15>

I/O

Bidirectional data bus.

57–65

PLL_LOCK

PLL Lock Indicator input from RF section. When High this signa

indicates that the PLL within the RF section is in lock and the master

clock inputs have stabilised.

DISCOP

Multi–purpose discrete output.

CLK_T

Master clock input (40MHz).

CLK_I

Inverted Master clock input.

SAMPCLK

Sample Clock output to the front end. Provides a 5.714MHz clock with a

4:3 mark–to–space ratio.

NBRAM / DISCIP4

Battery Backed RAM select input.

Multi–purpose discrete input.

Defines the state of the NRAM output in

Power Down mode.

SIGN0

SIGN0 input from the RF section.

MAG0

MAG0 input from the RF section.

SIGN1

SIGN1 input from a second, optional, RF section.

MAG1

MAG1 input from a second, optional, RF section.

DISCIP1

Multi–purpose discrete input.

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