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SM5846AP Scheda tecnica(PDF) 35 Page - Nippon Precision Circuits Inc

Il numero della parte SM5846AP
Spiegazioni elettronici  Multi-function Digital Filter
PDF  36 Pages
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Produttore elettronici  NPC [Nippon Precision Circuits Inc]
Homepage  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5846AP Scheda tecnica(HTML) 35 Page - Nippon Precision Circuits Inc

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SM5846AP
NIPPON PRECISION CIRCUITS—35
Serial data format
Address information is displayed in double-line cells of the table.
Test bits (mode flag 1 bit 4 and mode flag 3 bit 6) should be set to 0.
System Reset
When a reset is necessary
The device must be reset under the following condi-
tions.
s
When power is first applied
s
When the LRCI clock or system clock stop
Reset input conditions
The RST input is active LOW.
At power-ON reset, RST must go LOW and then go
HIGH after the XTI and LRCI clocks stabilize (reset
release).
Reset timing
The internal arithmetic registers and output sequence
are initialized on the rising edge of the LRCI clock
after reset release. The internal control flags and D-
ATT attenuation register are initialized after RST
goes LOW. Outputs DOL and DOR are tied LOW
while RST is LOW.
Power-ON reset using a capacitor
The RST input configuration is a Schmitt-trigger
input with a pull-up resistor, which means that a sim-
ple power-ON reset circuit can be made by connect-
ing a capacitor between RST and VSS as shown
below.
A 0.01 µF external capacitor is recommended. How-
ever, the time constant can be lengthened if longer
time is required for the XTI and LRCI clocks to sta-
bilize after power-ON.
The external capacitor discharges through the inter-
nal pull-up resistor at power-OFF as this is the only
possible discharge path. This could cause reset fail-
ure if power is reapplied while the external capacitor
is discharging. Therefore, a diode should be con-
nected between RST and VDD to quickly discharge
the capacitor and ensure correct power-ON reset
operation.
External power-ON reset circuit
Register
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
D-ATT attenuation
0
a1
a2
a3
a4
a5
a6
a7
Mode flag 1
1
0
SYNC
TEST1 = 0
HS
FSEL1
FSEL2
DEEM
Mode flag 2
1
1
MUTE
DITH
OBS
IBS1
IBS2
1
Mode flag 3
1
1
ASEL1
ASEL2
1
TEST2 = 0
1
0
‘
Internal Pull-up Register
C
External
Capacitor
Schmitt Buffer
RST
C
RST
Discharge
for Diode
Internal Pull-up Register
Schmitt Buffer
External
Capacitor



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